Switched Capacitor Circuits


Double sampling Sigma Delta ADC

Double sampling is a method to double the throughput of a switched capacitor circuit, without increasing the power consumption. However, traditional circuits don't use this technique because path mismatch between both sampling branches deteriorates the performance. For this problem we have proposed a solution, which consists in modifying the loop filter. This solution was also implemented in a prototype 16-bit ADC (photo).

Extended counting A/D conversion.

Extended Counting is a technique for high-accuracy A/D conversion. The methode is a combination of first-order Sigma Delta modulation and algorithmic A/D conversion. Its most intersting property is that the realisation requires only 1 operational amplifier and 1 comparator. The approach has an inherent trade-off between accuracy on the one hand and bandwidth on the other hand. This trade-off is similar as for Sigma Delta modulation. Unlike for (more common) sigma delta modulation the resulting A/D converter operates as a Nyquist-rate convertor. This way, this type of converter is very intuitive to use and can also easily be multiplexed. In the CAS-group various prototypes have been designed for various applications. The chip right-top is a 14-bit voice-band A/D-converter intended for use in ear prothesises (cochlear implants). A complete conversion cycle only takes 16 clock cycles. The circuit has a very low power consumption (150 uW) and operates at a supply voltage of only 1.2 Volt. The chip in the middle right is a programmable variant where the accuracy and the conversion speed are programmable. Here the accuracy can be set in a 16-18 bit range.
The chip bottom right is also using double sampling and has a conversion speed of 1 MHz at a 15-bit accuracy.

 

Pipelined A/D convertors

Pipelined A/D convertors can achieve a high conversion speed (several 100's MHz). To obtain good performance, it is necessary to build in tolerance against various non-idealities. E.g. the use of redundant comparators to eliminate the effect of comparator offsets is widely adopted. In this regard there are many possbilities with for instance the popular RSD (redundant signed digit) scheme. Also othe non-idealities such as capacitor mismatch of finite DC-gain of ther operational ampliers can be tackled through self-calibration. In the depicted chip (left) these techniques (digital self-calibration and comparator redundancy) are combined with a dedicated double sampling scheme.


Involved researchers: dr. ir. Jeroen De Maeyer, Prof. Pieter Rombouts