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Summary


Why analog design?

While today much signal processing is done in the digital domain, physical quantities usually are of an analog nature. Therefore interfacing between the analog and digital world is an essential task [1,3,4] and its precision is crucial to overall system performance. A blend of a high performance A/D front-end and sofisticated digital processing can be found in numerous modern systems, e.g. telecom applications, smart sensors, ...
In the past, analog IC design has been the playground of a few large companies and their standardized analog and conversion modules were used as such in many different applications. Nowadays, CMOS chip design has become available at a reasonable cost. Integration of digital and customized analog functions on a single (CMOS) chip is accessible even for smaller companies. In this context, analog modules are no longer standard off-the-shelf products but often are higly optimized for specific applications.

Benefits and challenges of integrated systems in CMOS

The higher integration density allows us to build systems with unprecedented performance by using sophisticated (signal) processing and circuit techniques.
Analog building blocks can be optimized for the given application since their loads are well-known and under control. So a huge increase in speed and/or significant reduction in power consumption may be achieved.

The wide availability at reasonable cost of CMOS chip fabrication and the ongoing evolution in technology represent a permanent challenge to the analog design community.

Imperfections of active as well as passive components (particullarly mismatch) limit system performance.
Strategies such as oversampling, dynamic element matching or self-calibration have been used to dramatically increased system performance.
Nowadays a considerable research effort is going on to refine and combine these methods in order to open the road to new applications.

Relevant publications

[11]
P. Rombouts, J. De Maeyer and L. Weyten, "A 250 kHz, 94 dB double-sampling Sigma Delta modulation A/D converter with a modified noise transfer function," IEEE Journal Solid-State Circuits, vol. 38, No. 10, pp. 1657-1662, Oct. 2003.
[10]
J. De Maeyer, P. Rombouts and L. Weyten, "Adressing static and dynamic errors in unit element multibit DACs," Electronics Letters, vol. 39, No. 14, pp. 1038-1039, 10th jul. 2003.
[9]
P. Rombouts, J. Raman and L. Weyten, "An approach to tackle quantisation noise folding in double-sampling Sigma Delta modulation A/D converters," IEEE Trans. Circuits Syst.-II, vol. 50, No. 4, pp. 157-163, Apr. 2003.
[8]
P. Rombouts, W. De Wilde and L. Weyten, "A 13.5-b 1.2-V micropower extended counting A/D converter," IEEE Journal Solid-State Circuits, vol. 36, No. 2, pp. 176-183, Feb. 2001.
[7]
P. Rombouts and L. Weyten, "A Study of Dynamic Element-Matching Techniques for 3-level Unit Elements," IEEE Trans. Circuits Syst.-II., vol. 47, No. 11, pp. 1177-1187, Nov. 2000.
[6]
P. Rombouts and L. Weyten, "Corrections to A Comment on `Interstage Gain Proration Technique for Digital-Domain Multistep ADC Calibration'," IEEE Trans. Circuits Syst.-II., vol. 46, No. 11, pp. 1449, Nov. 1999.
[5]
P. Rombouts and L. Weyten, "Comments on Interstage Gain Proration Technique for Digital-Domain Multistep ADC Calibration," IEEE Trans. Circuits Syst.-II., vol. 46, No. 8, pp. 1114-1116, Aug. 1999.
[4]
P. Rombouts, L. Weyten, J. Raman and S. Audenaert, "Capacitor Mismatch Compensation for the Quasi-Passive Switched-Capacitor DAC," IEEE Trans. Circuits Syst.-I, vol. 45, no. 1, Jan. 1998, pp. 68-71.
[3]
P. Rombouts and L. Weyten, "A Digital Error-Averaging Technique for Pipelined A/D Conversion," IEEE Trans.Circuits Syst.-II, vol. 45, no. 9, Sept. 1998, pp. 1321-1323.
[2]
P. Rombouts and L. Weyten, "Linearity improvement for the switched-capacitor DAC,'' Electron. Lett., vol. 32, No. 4, pp. 293-294, 15th February 1996.
[1]
L. Weyten and S. Audenaert, "Two-Capacitor DAC With Compensative Switching," Electron. Lett., vol. 31, No. 17, 1435-1436, 17th August 1995.